Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 17
UG482 (v1.9) December 19, 2016
Simulation
SecureIP models are encrypted versions of the Verilog HDL used for implementation of the
modeled block. SecureIP is an IP encryption methodology. To support SecureIP models, a
Verilog LRM - IEEE Std 1364-2005 encryption compliant simulator is required.
• A mixed-language simulator for VHDL simulation.
SecureIP models use a Verilog standard. To use them in a VHDL design, a mixed-language
simulator is required. The simulator must be able to simulate VHDL and Verilog
simultaneously.
• An installed GTP transceiver SecureIP model.
• The correct setup of the simulator for SecureIP use (initialization file, environment variables).
• The ability to run COMPXLIB, which compiles the simulation libraries (e.g., UNISIM,
SIMPRIMS) in the correct order.
• The correct simulator resolution (Verilog).
• The user guide of the simulator and UG626
, Synthesis and Simulation Design Guide provide a
detailed list of settings for SecureIP support.
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600