Xilinx 7 Series User Manual

18 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 1: Transceiver and Tool Overview
Ports and Attributes
There are no simulation-only ports on the GTPE2_COMMON and GTPE2_CHANNEL primitives.
GTPE2_COMMON Attributes
The GTPE2_COMMON primitive has attributes intended only for simulation. Table 1-2 lists the
simulation-only attributes of the GTPE2_COMMON primitive. The names of these attributes start
with SIM_.
Table 1-2: GTPE2_COMMON Simulation-Only Attributes
Attribute Type Description
SIM_PLL0REFCLK_SEL 3-bit
Binary
This attribute selects the reference clock source
used to drive PLL0 in simulation for designs where
PLL0 is always driven by the same reference clock
source. SIM_PLL0REFCLK_SEL allows for
simulation before and after the port swap changes.
This allows for the block to be simulated with the
correct clock source both before and after the port
swap. SIM_PLL0REFCLK_SEL must be set to the
same value as PLL0REFCLK SEL[2:0]. For
designs that require the reference clock source to
be changed on the fly, the port PLL0REFCLKSEL
is used instead to dynamically select the reference
clock source.
SIM_PLL1REFCLK_SEL 3-bit
Binary
This attribute selects the reference clock source
used to drive PLL1 in simulation for designs where
PLL1 is always driven by the same reference clock
source. SIM_PLL1REFCLK_SEL allows for
simulation before and after the port swap changes.
This allows for the block to be simulated with the
correct clock source both before and after the port
swap. SIM_PLL1REFCLK_SEL must be set to the
same value as PLL1REFCLK SEL[2:0]. For
designs that require the reference clock source to
be changed on the fly, the port PLL1REFCLKSEL
is used instead to dynamically select the reference
clock source.
SIM_RESET_SPEEDUP String If the SIM_RESET_SPEEDUP attribute is set to
TRUE (default), an approximated reset sequence is
used to speed up the reset time for simulations,
where faster reset times and faster simulation times
are desirable. If the SIM_RESET_SPEEDUP
attribute is set to FALSE, the model emulates
hardware reset behavior in detail.
SIM_VERSION String This attribute selects the simulation version to
match different steppings of silicon. The default
for this attribute is 1.0.
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600