Xilinx 7 Series User Manual

182 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
13. Deassert RXDLYEN for the master lane.
14. Assert RXPHALIGN for all slave lane(s). Hold this signal High until the rising edge of
RXPHALIGNDONE of the respective slave lane is observed.
15. Deassert RXPHALIGN for the slave lane in which the RXPHALIGNDONE is asserted.
16. When RXPHALIGN for all slave lane(s) are deasserted, assert RXDLYEN for the master lane.
This causes RXPHALIGNDONE of the master lane to be deasserted.
17. Wait until RXPHALIGNDONE of the master lane reasserts. Phase and delay alignment for the
multi-lane interface is complete. Continue to hold RXDLYEN for the master lane High to adjust
RXUSRCLK to compensate for temperature and voltage variations.
In a multi-lane application, it is necessary to start the RX alignment procedure on the interface after
RXELECIDLE is deasserted on any lane. The RX CDR of all lanes should be locked before starting
the RX alignment procedure. This requirement is to ensure that the RX recovered clocks and
RXUSRCLK are stable and ready before alignment.
When the RX elastic buffer is bypassed, data received from the PMA might be distorted due to
phase differences after conditions such as a GTP transceiver reset or rate change. If the received data
evaluated at the fabric interface is invalid on any lane, the RX alignment procedure should be
repeated for the interface after the RX CDR is locked on all lanes.
Using RX Buffer Bypass in Multi-Lane Auto Mode
When a multi-lane application requires RX buffer bypass, phase alignment can be performed
manually or automatically. This section describes the steps required to perform the multi-lane RX
buffer bypass alignment procedure automatically:
• Master: In a multi-lane application, the buffer bypass master is the lane that is the source of
RXOUTCLK.
• Slave: These are all the lanes that share the same RXUSRCLK/RXUSRCLK2, which is
generated from the RXOUTCLK of the buffer bypass master.
Figure 4-40 shows an example of buffer bypass master versus slave lanes.
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600