Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 183
UG482 (v1.9) December 19, 2016
RX Buffer Bypass
These GTP transceiver settings should be used to bypass the RX buffer:
• RXBUF_EN = FALSE.
• RX_XCLK_SEL = RXUSR.
• RXOUTCLKSEL = 010 to select the RX recovered clock as the source of RXOUTCLK.
• RXDDIEN = 1.
With the RX recovered clock selected, RXOUTCLK is to be used as the source of RXUSRCLK.
The user must ensure that RXOUTCLK and the selected RX recovered clock are running and
operating at the desire frequency. When the RX elastic buffer is bypassed, the RX phase alignment
procedure must be performed after these conditions:
• Resetting or powering up the GTP receiver.
• Resetting or powering up the PLL.
• Changing the RX recovered clock source or frequency.
• Changing the GTP RX line rate.
To set up RX buffer bypass in multi-lane auto mode, the following attributes should be set:
• RXSYNC_MULTILANE = 1
• RXSYNC_OVRD = 0
The ports should be set as shown in Figure 4-41.
X-Ref Target - Figure 4-40
Figure 4-40: Example of Buffer Bypass Master versus Slave Lanes
GTP RX
Lane 0
GTP RX
Lane 1
GTP RX
Lane 2
GTP RX
Lane 3
MMCM/
PLL
BUFG BUFG
RXUSRCLK
RXUSRCLK2
RXUSRCLK
RXUSRCLK2
RXUSRCLK
RXUSRCLK2
RXUSRCLK
RXUSRCLK2
RXOUTCLK
Master
Slave
Slave
Slave
UG482_c4_140_020613
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600