Xilinx 7 Series

184 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
Figure 4-42 shows the required steps to perform auto RX phase and delay alignment.
X-Ref Target - Figure 4-41
Figure 4-41: RX Buffer Bypass—Multi-Lane Auto Mode Port Connection
UG482_c4_141_020613
Master
RXSYNCMODE
RXSYNCALLIN
RXSYNCIN RXSYNCOUT
RXSYNCDONE
RXPHALIGNDONE
1'b1
RXDLYSRESET
Slave
RXSYNCMODE
RXSYNCALLIN
RXSYNCIN RXSYNCOUT
RXSYNCDONE
RXPHALIGNDONE
1'b0
RXDLYSRESET
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