Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 191
UG482 (v1.9) December 19, 2016
RX Clock Correction
X-Ref Target - Figure 4-44
Figure 4-44: Clock Correction Conceptual View
Write Operation
Driven by
XCLK
Read Operation
Driven by
RXUSRCLK
Normal Condition If RXUSRCLK and XCLK Are Exactly the Same Frequency
Pointer Difference is Always Same Between
READ Address and WRITE Address While
They Are Moving
Write Operation
Driven by
XCLK
Insert Special Character to
Realign Pointer Difference
to Normal Condition
UG482_c4_26_071612
Read Operation
Driven by
RXUSRCLK
Elastic Buffer Can Underflow When Read Clock Faster Than Write Clock
Pointer Difference is Getting Smaller
When READ Clock is Faster
Write Operation
Driven by
XCLK
Remove Special Character to
Realign Pointer Difference
to Normal Condition
Read Operation
Driven by
RXUSRCLK
Elastic Buffer Can Overflow When Read Clock Slower Than Write Clock
Pointer Difference is Getting Bigger
When WRITE Clock is Faster
Send Feedback

Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English