Xilinx 7 Series - Page 279

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 279
UG482 (v1.9) December 19, 2016
0015
(Cont’d)
12:6 R/W SAS_MAX_COM 6:0
67 67
68 68
69 69
70 70
71 71
71 71
73 73
74 74
75 75
76 76
77 77
78 78
79 79
80 80
81 81
82 82
83 83
84 84
85 85
86 86
87 87
88 88
89 89
90 90
91 91
92 92
93 93
94 94
95 95
96 96
97 97
98 98
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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