Xilinx 7 Series - Page 303

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 303
UG482 (v1.9) December 19, 2016
009C
(Cont’d)
5:0 R/W RXBUF_THRESH_UNDFLW 5:0
36 36
37 37
38 38
39 39
40 40
41 41
42 42
43 43
44 44
45 45
46 46
47 47
48 48
49 49
50 50
51 51
52 52
53 53
54 54
55 55
56 56
57 57
58 58
59 59
60 60
61 61
62 62
63 63
009D 15:12 R/W RXBUF_EIDLE_HI_CNT 3:0 0-15 0-15
009D 11:8 R/W RXBUF_EIDLE_LO_CNT 3:0 0-15 0-15
009D 7R/W RXBUF_ADDR_MODE 0
FULL 0
FAST 1
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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