Xilinx 7 Series - Page 306

306 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Appendix D: DRP Address Map of the GTP Transceiver
009D 0 R/W RX_DEFER_RESET_BUF_EN 0
FALSE 0
TRUE 1
009E 2 R/W RXBUF_RESET_ON_COMMAALIGN 0
FALSE 0
TRUE 1
009E 1 R/W RXBUF_RESET_ON_RATE_CHANGE 0
FALSE 0
TRUE 1
009E 0 R/W RXBUF_RESET_ON_CB_CHANGE 0
FALSE 0
TRUE 1
009F 8:0 R/W TXDLY_LCFG 8:0 0-511 0-511
00A0 8:0 R/W RXDLY_LCFG 8:0 0-511 0-511
00A1 15:0 R/W RXPH_CFG 15:0 0-65535 0-65535
00A2 7:0 R/W RXPH_CFG 23:16 0-255 0-255
00A3 15:0 R/W RXPHDLY_CFG 15:0 0-65535 0-65535
00A4 7:0 R/W RXPHDLY_CFG 23:16 0-255 0-255
00A5 13:0 R/W RX_DEBUG_CFG 13:0 0-16383 0-16383
00A6 9:0 R/W ES_PMA_CFG 9:0 0-1023 0-1023
00A7 13 R/W RXCDR_PH_RESET_ON_EIDLE 0 0-1 0-1
00A7 12 R/W RXCDR_FR_RESET_ON_EIDLE 0 0-1 0-1
00A7 11 R/W RXCDR_HOLD_DURING_EIDLE 0 0-1 0-1
00A7 5:0 R/W RXCDR_LOCK_CFG 5:0 0-63 0-63
00A8 15:0 R/W RXCDR_CFG 15:0 0-65535 0-65535
00A9 15:0 R/W RXCDR_CFG 31:16 0-65535 0-65535
00AA 15:0 R/W RXCDR_CFG 47:32 0-65535 0-65535
00AB 15:0 R/W RXCDR_CFG 63:48 0-65535 0-65535
00AC 15:0 R/W RXCDR_CFG 79:64 0-65535 0-65535
00AD 2:0 R/W RXCDR_CFG 82:80 0-7 0-7
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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