Xilinx Virtex UltraScale+ FPGAs

• Output voltage swing
• Jier (determinisc, random, peak-to-peak)
• Rise and fall mes
• Supply voltage and current
• Noise specicaon
• Duty cycle and duty-cycle tolerance
• Frequency stability
These characteriscs are selecon criteria when choosing an oscillator for a GTM transceiver
design. Figure 49 illustrates the convenon for the single-ended clock input voltage swing, peak-
to-peak. This gure is provided to show the contrast to the dierenal clock input voltage swing
calculaon shown in Figure 50, as used in the GTM transceiver poron of the UltraScale+ device
data sheets (see hp://www.xilinx.com/documentaon).
Figure 49: Single-Ended Clock Input Voltage Swing, Peak-to-Peak
+V
Single-Ended Voltage
0
MGTREFCLKP
MGTREFCLKN
X20931-053118
Figure 50 illustrates the dierenal clock input voltage swing, which is dened as MGTREFCLKP
- MGTREFCLKN.
Figure 50: Differential Clock Input Voltage Swing, Peak-to-Peak
+V
–V
0
MGTREFCLKP – MGTREFCLKN
V
IDIFF
X20932-053118
Figure 51 shows the rise and fall me convenon of the reference clock.
Chapter 5: Board Design Guidelines
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 121
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