Xilinx Virtex UltraScale+ FPGAs User Manual

Figure 8: Single External Reference Clock with Multiple Duals
GTM_DUAL
GTREFCLK
MGTREFCLKP
MGTREFCLKN
I
IB
IBUFDS_GTM
O
GTM_DUAL
GTREFCLK
GTM_DUAL
GTREFCLK
D(n+1)
D(n)
D(n-1)
X20215-061418
Note: The IBUFDS_GTM diagram in the above gure is a simplicaon. The output port ODIV2 is le
oang, and the input port CEB is set to logic 0.
These rules must be observed when sharing a reference clock to ensure that jier margins for
high-speed designs are met:
• The number of Duals above the sourcing Dual must not exceed one.
• The number of Duals below the sourcing Dual must not exceed one.
• The total number of Duals sourced by an external clock pin pair (MGTREFCLKP/
MGTREFCLKN) must not exceed three Duals.
The maximum number of Duals that can be sourced by a single clock pin pair is three (six
transceivers). Designs with more than three Duals require the use of mulple external clock pins
to ensure that the rules for controlling jier are followed. When mulple clock pins are used, an
external buer can be used to drive them from the same oscillator.
IMPORTANT
! Upon device conguraon, the clock output from the IBUFDS_GTM which takes inputs
from MGTREFCLKP and MGTREFCLKN can only be used as long as the GTPOWERGOOD signal has
already asserted High.
Ports and Attributes
The following table denes the clocking ports and aributes for the GTM_DUAL primive.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 17
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English