Xilinx Virtex UltraScale+ FPGAs User Manual

If the reset mode is defaulted to single mode, then you must:
1. Change reset mode to Sequenal mode.
2. Change all RXPMARESETMASK and RXPCSRESETMASK bits to High.
3. Wait another 300–500 ns.
4. Assert PLLRESET and GTRXRESET following the reset sequence described in the following
gure.
RECOMMENDED: Use the associated PLLLOCK from the LCPLL to release GTRXRESET from High to
Low. The RX reset state machine waits when GTRXRESET is detected High and starts the reset
sequence unl GTRXRESET is released Low.
Figure 19: GTM Receiver Initialization after Configuration
GTM Transceiver RX Reset in Response to GTRXRESET
Pulse in Full Sequential Mode
The GTM transceiver allows you to reset the enre RX at any me by sending GTRXRESET an
acve High pulse. These condions must be met when using GTRXRESET:
1. RXRESETMODE must be set to use sequenal mode.
2. All RXPMARESETMASK and RXPCSRESETMASK bits shold be held to High during the reset
sequence before RXRESETDONE is detected High.
3. The associated PLL must indicate locked.
4. The guideline for this asynchronous GTRXRESET pulse width is one period of the reference
clock.
Figure 20: GTM Receiver Reset after GTRXRESET Pulse in Full Sequential Reset
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 41
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English