Xilinx Virtex UltraScale+ FPGAs User Manual

Table 18: RX Initialization and Reset Attributes (cont'd)
Attribute Type Description
CH[0/1]_RST_LP_CFG3 16-bit Reserved. Use the recommended value from the
Wizard.
Bit Name Bit Field Description
RX_PRBS_RESET_LOOP_ID [15:12] Reserved. Use the recommended value from the
Wizard.
RX_PCS_RESET_LOOP_ID [11:8] Reserved. Use the recommended value from the
Wizard.
RX_FEC_RESET_LOOP_ID [7:4] Reserved. Use the recommended value from the
Wizard.
RX_EYESCAN_RESET_LOOP_ID [3:0] Reserved. Use the recommended value from the
Wizard.
CH[0/1]_RST_LP_ID_CFG0 16-bit Reserved. Use the recommended value from the
Wizard.
Bit Name Bit Field Description
RX_PCS_LOOPER_END_ID [15:12] Reserved. Use the recommended value from the
Wizard.
RX_PCS_LOOPER_START_ID [11:8] Reserved. Use the recommended value from the
Wizard.
RX_PMA_LOOPER_END_ID [7:4] Reserved. Use the recommended value from the
Wizard.
RX_PMA_LOOPER_START_ID [3:0] Reserved. Use the recommended value from the
Wizard.
CH[0/1]_RST_LP_CFG4 16-bit Reserved. Use the recommended value from the
Wizard.
Bit Name Bit Field Description
BYP_HDSHK_RX_PCS_RESET_LOOP [4] Reserved. Use the recommended value from the
Wizard.
BYP_HDSHK_TX_ADAPT_RESET_LOOP [1] Reserved. Use the recommended value from the
Wizard.
GTM Transceiver RX Reset in Response to Completion
of Configuration
The RX reset sequence shown in Figure 18 is not automacally started to follow global GSR.
These condions must be met:
1. RXRESETMODE must be set to sequenal mode.
2. GTRXRESET must be used.
3. All RXPMARESETMASK and RXPCSRESETMASK bits should be set to High.
4. GTRXRESET cannot be driven Low unl the associated PLL is locked.
5. Ensure that GTPOWERGOOD is High before releasing PLLRESET and GTRXRESET.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 40
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English