Xilinx Virtex UltraScale+ FPGAs User Manual

Figure 18: GTM Transceiver RX Reset State Machine Sequence
Wait until
GTRXRESET from
High to Low
GTRXRESET
High
RX PMA Top
Reset
RXPMARESETMASK[0]
= 1?
RXPMARESETMASK[1]
= 1?
RX ADC CLKGEN
Reset
Yes
No
RXPMARESETMASK[2]
= 1?
RX DSP Reset
Yes
No
RXPMARESETMASK[3]
= 1?
RX DFE Reset
Yes
Yes
No
No
RXRESETDONE
High
RXPMARESETMASK[4]
= 1?
RX Adapt Reset
Yes
No
RXPMARESETMASK[5]
= 1?
RX CDR PH Reset
Yes
No
RXPMARESETMASK[6]
= 1?
RX CDR FR Reset
Yes
No
RXPCSRESETMASK[0]
= 1?
RX Eye Scan
Reset
Yes
No
RXPCSRESETMASK[1]
= 1?
RX FEC Reset
Yes
No
RXPCSRESETMASK[2]
= 1?
RX PCS Top Reset
Yes
No
RXPCSRESETMASK[3]
= 1?
RX PRBS Counter
Reset
Yes
No
Wait for
RXUSERRDY = 1
X20906-053118
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 35
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English