Xilinx Virtex UltraScale+ FPGAs User Manual

TX Rate Change
When a rate change is performed, a full TX sequenal reset is required aer the rate aributes
have been updated.
TX Parallel Clock Source Reset
The clocks driving TXUSRCLK must be stable for correct operaon. Perform a TX PCS reset aer
the clock source re-locks.
RX Initialization and Reset
The GTM transceiver RX uses a reset state machine to control the reset process. Due to its
complexity, the GTM transceiver RX is paroned into more reset regions than the GTM
transceiver TX. The paron allows RX inializaon and reset to be operated in either sequenal
mode, as shown in the following gure, or single mode:
1. RX in Sequenal Mode: To inialize the GTM transceiver RX, RXRESETMODE must be set to
sequenal mode. The RX components that are required to be rest are determined by seng
the appropriate RXPMARESETMASK and RXPCSRESETMASK bits to High. The reset
sequence is then triggered by toggling GTRXRESET and then internal component resets are
triggered sequenally. The reset state machine executes the reset sequence as shown in the
following gure, covering the enre RX PMA and RX PCS. During normal operaon, the reset
state machine runs unl RXRESETDONE transions from Low to High.
2. RX in Single Mode: When the GTM transceiver RX is in single mode, RXRESETMODE must
be set to single mode. The RX components that are required to be rest are determined by
seng the appropriate RXPMARESETMASK and RXPCSRESETMASK bits to High. The reset
sequence is then triggered by toggling GTRXRESET and the internal component resets are
triggered simultaneously. In addion, RXADAPTRESET, RXADCCLKGENRESET,
RXBUFRESET, RXCDRFRRESET, RXCDRPHRESET, RXDFERESET, RXDSPRESET,
RXEYESCANRESET, RXFECRESET, RXPCSRESET, RXPMARESET and RXPRBSCNTRESET
pins are available to reset those components directly in single mode.
In either sequenal mode or single mode, the RX reset state machine does not reset the PCS
unl RXUSERRDY goes High. Drive RXUSERRDY High aer all clocks used by the applicaon,
including RXUSRCLK, are shown to be stable.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 34
Send Feedback

Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English