Xilinx Virtex UltraScale+ FPGAs User Manual

Table 18: RX Initialization and Reset Attributes (cont'd)
Attribute Type Description
CH[0/1]_RST_TIME_CFG4 16-bit Reserved. Use the recommended value from the
Wizard.
Bit Name Bit Field Description
RX_PCS_RESET_TIME [14:10] Reserved. Represents the time duration to apply an RX
PCS reset. Use the recommended value from the
Wizard. Must be a non-zero value when
RXPCSRESETMASK[2] is High and GTRXRESET initiates
the reset process.
RX_FEC_RESET_TIME
[9:5] Reserved. Represents the time duration to apply an RX
buffer reset. Use the recommended value from the
Wizard. Must be a non-zero value when
RXPCSRESETMASK[1] is High and GTRXRESET initiates
the reset process.
RX_EYESCAN_RESET_TIME
[4:0] Reserved. Represents the time duration to apply an
eye scan reset. Use the recommended value from the
Wizard. Must be a non-zero value when
RXPCSRESETMASK[0] is High and GTRXRESET initiates
the reset process.
CH[0/1]_RST_TIME_CFG5
16-bit Reserved. Use the recommended value from the
Wizard.
Bit Name Bit Field Description
RX_PRBS_RESET_TIME [4:0] Reserved. Represents the time duration to apply a
PRBS counter reset. Use the recommended value from
the Wizard. Must be a non-zero value when
RXPCSRESETMASK[3] is High and GTRXRESET initiates
the reset process.
CH[0/1]_RST_LP_CFG1
16-bit Reserved. Use the recommended value from the
Wizard.
Bit Name Bit Field Description
RX_DSP_RESET_LOOP_ID [15:12] Reserved. Use the recommended value from the
Wizard.
RX_ADC_CLKGEN_RESET_LOOP_ID [11:8] Reserved. Use the recommended value from the
Wizard.
RX_DFE_RESET_LOOP_ID [7:4] Reserved. Use the recommended value from the
Wizard.
RX_PMA_RESET_LOOP_ID [3:0] Reserved. Use the recommended value from the
Wizard.
CH[0/1]_RST_LP_CFG2 16-bit Reserved. Use the recommended value from the
Wizard.
Bit Name Bit Field Description
RX_CDRFREQ_RESET_LOOP_ID [15:12] Reserved. Use the recommended value from the
Wizard.
RX_CDRPHASE_RESET_LOOP_ID [11:8] Reserved. Use the recommended value from the
Wizard.
RX_ADAPT_RESET_LOOP_ID [3:0] Reserved. Use the recommended value from the
Wizard.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 39
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English