Xilinx Virtex UltraScale+ FPGAs User Manual

The following table lists aributes required by GTM transceiver RX inializaon. In general cases,
the reset me required by the RX PMA or the RX PCS varies depending on line rate. The factors
aecng PMA reset me and PCS reset me are the user-congurable aributes
RX_PMA_RESET_TIME, RX_DFE_RESET_TIME, RX_ADAPT_RESET_TIME,
RX_DSP_RESET_TIME, RX_ADC_CLKGEN_RESET_TIME, RX_CDRFREQ_RESET_TIME,
RX_CDRPHASE_RESET_TIME, RX_PCS_RESET_TIME, RX_FEC_RESET_TIME,
RX_PRBS_RESET_TIME and RX_EYESCAN_RESET_TIME.
Table 18: RX Initialization and Reset Attributes
Attribute Type Description
CH[0/1]_RST_TIME_CFG2 16-bit Reserved. Use the recommended value from the
Wizard.
Bit Name Bit Field Description
RX_ADAPT_RESET_TIME [14:10] Reserved. Represents the time duration to apply an RX
adapt reset. Use the recommended value from the
Wizard. Must be a non-zero value when
RXPMARESETMASK[4] is High and GTRXRESET initiates
the reset process.
RX_DSP_RESET_TIME
[9:5] Reserved. Represents the time duration to apply an RX
DSP reset. Use the recommended value from the
Wizard. Must be a non-zero value when
RXPMARESETMASK[2] is High and GTRXRESET initiates
the reset process.
RX_ADC_CLKGEN_RESET_TIME
[4:0] Reserved. Represents the time duration to apply an RX
ADC CLKGEN reset. Use the recommended value from
the Wizard. Must be a non-zero value when
RXPMARESETMASK[1] is High and GTRXRESET initiates
the reset process.
CH[0/1]_RST_TIME_CFG3
16-bit Reserved. Use the recommended value from the
Wizard.
Bit Name Bit Field Description
RX_CDRFREQ_RESET_TIME [14:10] Reserved. Represents the time duration to apply an RX
CDR FR reset. Use the recommended value from the
Wizard. Must be a non-zero value when
RXPMARESETMASK[5] is High and GTRXRESET initiates
the reset process.
RX_CDRPHASE_RESET_TIME
[9:5] Reserved. Represents the time duration to apply an RX
CDR PH reset. Use the recommended value from the
Wizard. Must be a non-zero value when
RXPMARESETMASK[6] is High and GTRXRESET initiates
the reset process.
CH[0/1]_RST_TIME_CFG1
16-bit Reserved. Use the recommended value from the
Wizard.
Bit Name Bit Field Description
RX_DFE_RESET_TIME [14:10] Reserved. Represents the time duration to apply an RX
DFE reset. Use the recommended value from the
Wizard. Must be a non-zero value when
RXPMARESETMASK[3] is High and GTRXRESET initiates
the reset process.
RX_PMA_RESET_TIME
[9:5] Reserved. Represents the time duration to apply an RX
PMA reset. Use the recommended value from the
Wizard. Must be a non-zero value when
RXPMARESETMASK[0] is High and GTRXRESET initiates
the reset process.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 38
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English