Xilinx Virtex UltraScale+ FPGAs User Manual

Table 46: TX Configurable Driver Ports (cont'd)
Port Dir
Clock
Domain
Description
CH[0/1]_TXMUXDCDORWREN Input Async Reserved. Use the recommended value from the Wizard.
The following table denes the TX congurable driver aributes.
Table 47: TX Configurable Driver Attributes
Attribute Type Description
CH[0/1]_TX_ANA_CFG1 16-bit Reserved.
Bit Name Address Description
TXMODSEL [7] Driver output modulation control:
1’b0: PAM4 modulation.
1’b1: NRZ modulation.
CH[0/1]_TX_DRV_CFG0 16-bit Reserved.
Bit Name Address Description
TXEMPMAIN_INDEP [0] Allows independent control of the main cursor:
1’b0: The CH[0/1]_TXEMPMAIN coefficient is
automatically determined.
1’b1: CH[0/1]_TXEMPMAIN coefficient can be
independently set by the CH[0/1]_TXEMPMAIN
pins within the range specified in the pin
description.
Use Modes
The GTM TX has the ability to transmit serial data using two dierent modulaon schemes: NRZ
and PAM4. NRZ signals contains one bit of informaon per symbol, while PAM4 signals contain
two bits of informaon per symbol. Using PAM4 modulaon doubles the transmied data
bandwidth while maintaining the same unit interval (UI). To program the GTM TX to a desired
signal modulaon mode, the user must congure the aribute TXMODSEL for CH0 or CH1.
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 83
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English