Z8
®
CPU
User Manual
UM001604-0108 Power-Down Modes
113
external clock frequency when this bit is set (D1 = 1). Using this bit together with D7 of
PCON helps further lower EMI (D7 (PCON) = 0, D1 (SMR) = 1). The default setting is
zero.
Stop Mode Recovery Source—The D2, D3, and D4 bits of the SMR specify the
wake-up source of the stop-recovery and (Table 22 and Figure 104 on page 114).
Stop Mode Recovery Delay Select—This D5 bit, if High, enables the T
POR
RESET
delay after Stop Mode Recovery. The default configuration of this bit is 1. If the fast wake
up is selected, the Stop Mode Recovery source is kept active for at least 5 TpC.
Stop Mode Recovery Edge Select—A 1 in this D6 bit position indicates that a high
level on any one of the recovery sources wakes the Z8
®
CPU from STOP mode. A 0 indi-
cates low-level recovery. The default is 0 on POR (see Figure 104 on page 114).
Cold or Warm Start—This D7 bit is set by the device upon entering STOP mode. A 0 in
this bit (cold) indicates that the device reset by POR/WDT RESET. A 1 in this bit (warm)
indicates that the device awakens by a SMR source.
Table 22. Stop Mode Recovery Source
SMR: 432
Description of OperationD4 D3 D2
0 0 0 POR and/or external reset recovery.
0 0 1 P30 transition.
0 1 0 P31 transition (not in Analog Mode).
0 1 1 P32 transition (not in Analog Mode).
1 0 0 P33 transition (not in Analog Mode).
1 0 1 P27 transition.
1 1 0 Logical NOR of P20 through P23.
1 1 1 Logical NOR of P20 through P27.
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