ZiLOG Z8 Series - Page 160

Z8
®
CPU
User Manual
UM001604-0108 Instruction Set
153
dst ← src and
r ← r + 1 or
rr ←rr + 1
lrr Ir 93
NOP FF ––––––
OR dst, src
dst ← dst OR src
†4[ ]–[[0––
POP dst R 50 ––––––
dst ← @SP
and SP ← SP + 1
IR 51
PUSH src R 70 ––––––
SP ← SP–1
and @SP ← src
IR 71
RCF
C ← 0
C F 0–––––
RET
PC ← @SP;
SP ← SP + 2
A F ––––––
RL dst R
IR
90
91
[[[[––
RLC dst R
IR
10
11
[[[[––
RR dst R
IR
E 0
E 1
[[[[––
RRC dst R C 0 [[[[––
IR C 1
SBC dst, src
dst ← dst–src–C
† 3[ ] [[[[1[
SCF
C ← 1
D F 1–––––
SRA dst R D 0 [[[0––
IR D 1
Table 39. Summary of Z8 Instruction Set (Continued)
Instruction and Operation
Address Mode
Op Code
Byte (Hex)
Flags Affected
dst src C Z S V D H
C
7
0
C
7
0
C
7
0
C
7
0
C
7
0