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CPU

User Manual

UM001604-0108 Instruction Set

154

SRP dst

RP ← src

Im 31 ––––––

STOP 6 F ––––––

SUB dst, src

dst ← dst–src

† 2[ ] [[[[1[

SWAP dst R

X[ [X––

TCM dst, src

(NOT dst) AND src

†6[ ]–[[0––

TM dst, src

dst AND src

†7[ ]–[[0––

WDh 4 F – X X X – –

WDT 5 F – X X X – –

XOR dst, src

dst AND src

XOR src

†7[ ]–[[0––

*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The first opcode

nibble is found in the instruction set table above. The second nibble is expressed symbolically by a ‘[ ]’ in this table,

and its value is found in the following table to the left of the applicable addressing mode pair. For example, the opcode

of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13.

Table 39. Summary of Z8 Instruction Set (Continued)

Instruction and Operation

Address Mode

Op Code

Byte (Hex)

Flags Affected

dst src C Z S V D H

ZiLOG Z8 Series User Manual

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