Z8
®
CPU
User Manual
UM001604-0108 Instruction Description
168
Complement
Syntax
COM dst
Instruction Format
Operation
dst ← NOT dst
The contents of the destination operand are complemented (one’s complement). All 1 bits
are changed to 0, and all 0 bits are changed to 1.
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the
destination Working Register operand is specified by adding
1110b (Eh) to the high nibble
of the operand. For example, if Working Register R12 (CH) is the destination operand, then
ECh is used as the destination operand in the Op Code.
Example 1
If Register 08h contains 24h (00100100b), the statement:
COM 08h
Op Code: 60 08
leaves the value DBh (11011011) in Register 08h. The S Flag is set, and the Z and V
Flags are cleared.
Cycles
OPC
(Hex)
Address Mode
dst
OPC dst
660 R
661 IR
Flag Description
C Unaffected
Z Set if the result is zero; cleared otherwise.
S Set if result bit 7 is set; cleared otherwise.
V Always reset to 0.
D Unaffected
H Unaffected
Edst
Note:
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