MC81F4204
104 April 24, 2012 Ver.1.41
T2SCR
TIMER 2 STATUS AND CONTROL REGISTER (T2SCR) 00B6H
To enable the timer 2 match interrupt, you must set “1” to T2MIE.
When the timer 2 match interrupt sub-routine is serviced, the timer 1 match interrupt request flag bit,
T2MIR(IRQH.3), is automatically cleared.
To enable the timer 2 overflow interrupt, you must set “1” to T2OVIE.
When the timer 2 overflow interrupt sub-routine is serviced, the timer 2 overflow interrupt request flag
bit, T2OVIR(IRQH.2), is automatically cleared.
7 6 5 4 3 2 1 0
T2SCR
- – T2MS T2CC T2CS
Reset value: 00H
- – R/W R/W R/W R/W R/W R/W
–
bit7 - bit6 Not used for MC81F4204
0: Interval mode (T2O)
T2MS
Timer 2 Mode Selection Bit
1: Capture mode (OVF can occur)
0: No effect
T2CC
Timer 2 Counter Clear Bit
1: Clear the Timer 2 counter (When
write, automatically cleared “0” after
being cleared counter)
0000: Counter stop
0001: Not available
0010: Not available
0011: Not available
0100: Not available
0101: External clock (EC2) rising edge
0110: External clock (EC2) falling edge
0111: Not available
1000: fxx/1
1001: fxx/2
1010: fxx/4
1011: fxx/8
1100: fxx/16
1101: fxx/64
1110: fxx/256
T2CS
Timer 2 Clock Selection Bits
1111: fxx/1024
Note :
You must set the T2CC(T2SCR.4) bit after set T2DR register. The timer 2 counter value is
compared with timer 2 buffer register instead of T2DR. And T2DR value is copied to timer 2
buffer.
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