ABOV SEMICONDUCTOR MC81F4204 - 22.4 Watchdog Timer Reset

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MC81F4204

124 April 24, 2012 Ver.1.41

22.4 Watch Dog Timer Reset

See ‘15. WATCH DOG TIMER’ on page 93.

Figure 22-3 Reset circuit Example

Main Page

Default Chapter3
- Revision History3
- Table of Contents6
1 Overview9
- Description9
- Features9
- Development Tools10
- Ordering Information11
2 Block Diagram12
3 Pin Assignment13
- Pin- PDIP/SOP/TSSOP13
- Pin- QFN14
- Pin- PDIP/SOP/TSSOP14
- Summary15
4 Package Diagram16
- Pdip- Mc81F4204B16
- Sop - Mc81F4204D16
- Tssop - Mc81F4204W17
- Qfn - Mc81F4204U18
- Pdip - Mc81F4204V18
- Sop - Mc81F4204M19
- Tssop - Mc81F4204R19
5 Pin Description20
6 Port Structure23
7 Electrical Characteristics26
- Absolute Maximum Ratings26
- Recommended Operating Conditions26
- A/D Converter Characteristics27
- DC Electrical Characteristics28
- DC Electrical Characteristics (Continued)29
- Input/Output Capacitance29
- Serial I/O Characteristics30
- Data Retention Voltage in Stop Mode32
- LVR (Low Voltage Reset) Electrical Characteristics33
- POR (Power on Reset) Electrical Characteristics33
- Main Clock Oscillator Characteristics34
- External RC Oscillation Characteristics35
- Internal RC Oscillation Characteristics36
- Main Oscillation Stabilization Time36
- Operating Voltage Range37
- Typical Characteristics38
8 Rom Option42
- Read Timing43
9 Memory Organization44
- Registers44
- Program Memory48
- Data Memory51
- User Memory51
- Stack Area52
- Control Registers ( SFR )52
- Addressing Modes57
10 I/O Ports64
- R0 Port Registers65
- R1 Port Registers69
- R3 Port Registers73
11 Interrutp Controller75
- Registers76
- Interrupt Sequence78
- BRK Interrupt81
- Shared Interrupt Vector81
- Multi Interrupt82
- Interrupt Vector & Priority Table83
12 External Interrupts84
- Registers84
- Procedure87
13 Oscillation Circuits88
- Main Oscillation Circuits88
- PCB Layout89
14 Basic Interval Timer90
- Registers91
15 Watch Dog Timer93
- Registers94
16 Timer 0/195
- Registers95
- Timer 0 8-Bit Mode99
- Timer 1 8-Bit Mode101
17 Timer 2103
- Registers103
- Timer 2 8-Bit Mode105
18 High Speed PWM107
- Registers109
19 Buzzer111
- Registers112
- Frequency Table113
20 Bit Adc115
- Registers116
- Procedure117
- Conversion Timing117
- Internal Reference Voltage Levels118
- Recommended Circuit118
21 Serial I/O Interface119
- Registers120
- Procedure121
22 Reset122
- Reset Process122
- Reset Sources123
- Reset Circuit123
- Watch Dog Timer Reset124
- Power on Reset125
- Low Voltage Reset125
23 Power down Operation126
- Sleep Mode126
- Stop Mode128
- Sleep Vs Stop131
- Changing the Stabilizing Time132
- Minimizing Current Consumption132
24 Emulator134
25 In System Programming137
- Getting Started137
- Basic ISP S/W Information138
- Hardware Conditions to Enter the ISP Mode140
- Entering ISP Mode at Power on Time141
- USB-SIO-ISP Board142
26 Instruction Set143
- Terminology List143
- Instruction Map144
- Instruction Set145

ABOV SEMICONDUCTOR MC81F4204 - 22.4 Watchdog Timer Reset

Table of Contents