ABOV SEMICONDUCTOR MC81F4204 - 11. Interrupt Controller

MC81F4204
April 24, 2012 Ver.1.41 75
11. INTERRUTP CONTROLLER
Watchdog Timer Interrupt
Timer0 matchInterrupt
SIO Interrupt
SIOIR
SIOIE
T0MIR
T0OVIR
T0OVIE
T0MIE
Timer0 overflow Interrupt
Timer1 matchInterrupt
T1MIR
T1OVIR
T1OVIE
T1MIE
Timer1 overflow Interrupt
WDTIR
WDTIE
Priority Control
Release STOP/SLEEP
I-flag
Interrupt
Master
Enable
Flag
To CPU
Interrupt
Vector
Address
Generator
Basic Timer Interrupt BTIR
BTIE
Timer2 matchInterrupt T2MIR
T2OVIR
T2OVIF
T2MIE
Timer2 overflow Interrupt
INTFH
Interrupt
Flag
External Interrupt 3
External Interrupt 1
EXT1IR
EXT3IR
External Interrupt 6
External Interrupt 5
EXT5IR
EXT6IR
EXT1IE
Interrupt
Request
Interrupt
Enable
EXT3IE
EXT5IE
EXT6IE
External Interrupt 2
External Interrupt 0
EXT0IR
EXT2IR
External Interrupt 7
External Interrupt 4
EXT4IR
EXT7IR
External Interrupt 9
External Interrupt 8
EXT8IR
EXT9IR
EXT2IE
EXT0IE
EXT7IE
EXT4IE
EXT9IE
EXT8IE
EINTF
Interrupt
Flag
External Interrupt 10 EXT10IR
EXT10IE
External Interrupt 11 EXT11IR
EXT11IE
The MC81F4204 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request
flags of IRQH, IRQL, Priority circuit, and Master enable flag (“I” flag of PSW). And 21 interrupt
sources are provided.
The interrupt vector addresses are shown in ‘
11.6 Interrupt Vector & Priority Table’ on page 83.
Interrupt enable registers are shown in next paragraph. These registers are composed of interrupt
enable flags of each interrupt source and these flags determine whether an interrupt will be accepted
or not. When the enable flag is “0”, a corresponding interrupt source is disabled.
Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
Figure 11-1 Block Diagram of Interrupt