ABOV SEMICONDUCTOR MC81F4204 - 20.1 Registers (ADMR, ADDRH, ADDRL)

MC81F4204
116 April 24, 2012 Ver.1.41
20.1 Registers
ADMR
A/D MODE REGISTER 00BDH
7 6 5 4 3 2 1 0
ADMR
SSBIT EOC ADCLK ADCH
Reset value: 00H
R/W R R/W R/W R/W R/W R/W R/W
After reset, the start/stop bit is turned off. You can select only one analog input channel at a time.
Other analog input (AD0-AD8,AD14,BGR) can be selected dynamically by manipulating the ADCH.
And the pins not used for analog input can be used for normal I/O function.
0: Stop operation
SSBIT
Start or Stop bit
1: Start operation
0: Conversion not complete
EOC
End of Conversion
1: Conversion complete
ADCLK
A/D Clock Selection
00: fxx/1
01: fxx/2
10: fxx/4
11: fxx/8
ADCH
A/D Input Pin Selection
0000: AN0
0001: AN1
0010: AN2
0011: AN3
0100: AN4
0101: AN5
0110: AN6
0111: AN7
1000: AN8
1001: Not available
1010: Not available
1011: Not available
1100: Not available
1101: Not available
1110: AN14
1111: BGR
ADDRH
A/D CONVERTER DATA HIGH REGISTER 00BEH
7 6 5 4 3 2 1 0
ADDRH
.11 .10 .9 .8 .7 .6 .5 .4
Reset value: XXH
R R R R R R R R
A 8-bit data register for higher 8-bits of the 12-bit ADC result.
ADDRL
A/D CONVERTER DATA LOW REGISTER 00BFH
7 6 5 4 3 2 1 0
ADDRL
.3 .2 .1 .0 - - - -
Reset value: X-H
R R R R R R R R