ABOV SEMICONDUCTOR MC81F4204 - 12. External Interrupts; 12.1 Registers (EINT0 H, EINT0 L, EINT1)

MC81F4204
84 April 24, 2012 Ver.1.41
12. EXTERNAL INTERRUPTS
The external interrupt pins are edge triggered depending on the ‘external interrupt registers’.
The edge detection of external interrupt has three transition activated mode: rising edge, falling edge,
and both edge.
12.1 Registers
EINT0H – EXT 2~5 / R04~R07
R0 PORT EXTERNAL INTERRUPT ENABLE HIGH REGISTER 00CAH
A reset clears the EINT0H register to ‘00H’, disables EXT5-EXT2 interrupt. You can use EINT0H
register setting to select Disable interrupt or Enable interrupt (by falling, rising, or both falling and
rising edge).
7 6 5 4 3 2 1 0
EINT0H
EXT5IE EXT4IE EXT3IE EXT2IE
Reset value: 00H
R/W R/W R/W R/W R/W R/W R/W R/W
EXT5IE
R07/EXT5 External Interrupt Enable Bits
EXT4IE
R06/EXT4 External Interrupt Enable Bits
EXT3IE
R05/EXT3 External Interrupt Enable Bits
EXT2IE
R04/EXT2 External Interrupt Enable Bits
00: Disable Interrupt
01: Enable Interrupt by falling edge
10: Enable Interrupt by rising edge
11: Enable Interrupt by both falling and
rising edge