MC81F4204
4 April 24, 2012 Ver.1.41
Add “16TSSOP” at 16pin pin assignment page.
Remove fxt(sub-clock source) at block diagrams and register descriptions of T0/1/2 and Buzzer.
VERSION 1.21 (July 7, 2009)
“25.3 Hardware Conditions to Enter the ISP Mode” is updated.
Notes of R35 port control registers are updated.
R3CONH, R3CONL register’s address are corrected at “Table 9-4 Control Register 4/4”
“R1 PORT PULL-UP ENABLE REGISTER table” is corrected.
VERSION 1.2 (June 29, 2009)
Remove ‘WDT’ at “Stop release” description. ‘WDT’ is not a release source of STOP mode.
Change “fxin” to “fbuz” at buzzer frequency calculation in “BUZZER” chapter.
VERSION 1.1 (June 17, 2009)
Add rom writing endurance at features.
Remove 16 bit mode at Timer0.
VERSION 1.0 (June 15, 2009)
Remove “preliminary”.
Some errata are fixed.
Add “Buzzer frequency table”.
VERSION 0.81 Preliminary (April 28, 2009)
Delete a note1 at ’20.5 recommended circuit’.
VERSION 0.8 Preliminary (April 16, 2009)
Add a sub-chapter ‘Changing the stabilizing time’ at the chapter ‘Power down operation’.
Add a note for R33/R34 ports after R3CONH description.
One of BIT’s clock source ‘2048’ is changed to ‘1024’.
VERSION 0.7 Preliminary (April 7, 2009)
Description of SIO procedure is updated.
Description of ISP chapter is updated.
VERSION 0.6 Preliminary (April 1, 2009)
Chapter ‘7.ELECTICAL CHARICTORISTICS’ is updated.
VERSION 0.5 Preliminary (March 5, 2009)
The SCLK pin for ISP is moved to R11 port.
Note for ADC recommended circuit is changed.
VERSION 0.4 Preliminary (February 12, 2009)
Correct 16 SOP package diagram.
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