ACT apricot - Page 138

SERIAL INTERFACE
Error flags associated with each receive character are also
buffered by a
similar arrangement. These are loaded into the
register of a parallel receive error FIFO stack at the same
time as the character. Each time the receive character is
shifted
through the character FIFO stack, the error flags are
moved accordingly. The top of the receive error FIFO stack
is one of the Read Registers.
The contents of this Read Register reflect the status of the
character stored in the receive buffer, but may also contain
any receiver overrun and pari ty errors received from
previous characters. These two error conditions remain
within the status register, even when new character error
flags are loaded,
until cleared by an error reset command.
If the character FIFO stack is full (i.e. contains three
characters) and the CPU fails to read the character within
the receive buffer before another receive character is
supplied
to the stack, the last character placed in the stack
is overwritten with the new character, and the receiver
overrun flag is recorded
in the corresponding register in the
receive error FIFO stack. The first two characters in the
stack are never overwritten, even if more characters are
received;
the last character is continuously overwritten.
Error
conditions stored in the FIFO stack can be
programmed to generate an interrupt to the CPU, on being
loaded
into the Read Register at the top of the stack.
In
the asynchronous mode~ using 8 bits per character, the
serial receive data is stripped of the start, stop and parity
bits, prior to being supplied to the serial shift register. For
character
lengths of less than 8 bits, the receiver circuits
automatically insert logic l's in the most significant places
to assemble a byte of data, if a parity bit is not included with
the character. If a parity bit is included, the parity bit is also
assembled
with the bits of the character, with any
remaining bits set to logic 1. For example, a 5-bit receive