ACT apricot - Page 147

SERIAL INTERFACE
Write Register 1
I
07
1
06
1
05
1
04
1
03
1
02
1 01 1 00 I WRl
~
I LEXt. Int Enable
L
TX
Int Enable
Status affects vector
(Channel B only)
Rx In t can trol
o 0 Mask Rx Interrupts.
o 1 Interrupt on 1st. Rx character.
I 0 Interrupt on all Rx characters,
parity affects vector.
1 1 Interrupt on all Rx characters,
parity does not affect vector.
Ready Control (ch.A only)
Ready on Rx/Tx
Ready Function
Ready Enable
Ext. Int Enable {DO}. The logic state of this bit determines
whether the External/Status interrupts are enabled (logic
high)
or masked (logic low). If enabled, an interrupt is
produced as a result of the following conditions.
1. Transitions on the modem control lines; DCD, CTS,
or SYNC.
2.
Detecting a break or abort condition in the receive
data.
3.
At the start of transmission of either CRC or sync
characters, in synchronous modes, when the Transmit
Underrun/EOM latch becomes set.
Tx Int Enable {Dl}. The logic state on this bit determines
whether the transmit interrupt is enabled (logic high) or
masked (logic low). If enabled, an interrrupt is produced
when the transmit buffer becomes empty.