Allen-Bradley SLC 500 Series - Page 238

Publication 1747-RM001G-EN-P - November 2008
11-6 Understanding Interrupt Routines
Subroutine File 4 - Executed for Error 0020h
If the overflow trap bit, S:5/0 is set, counter C5:0 increments.
If the count of C5:0 is 4 or less, the overflow trap, S:5/0 is cleared, the major
error halted bit S:1/13 is cleared, and the processor remains in the REM Run
mode. If the count is equal to 5, the processor sets S:5/0 and S:1/13 and
enters the Fault mode.
Subroutine file 5 is executed if the control register error bit S:5/2 is set.
EQU
EQUAL
Source A C5:0.ACC
0
Source B 5
END
S:5
0
S:5
(U)
0
RET
RETURN
S:1
(U)
13
RET
RETURN
SBR
SUBROUTINE
S:5
0
CTU
COUNT UP
Counter
Preset
Accum
S5:0
120
0
C5:0
(U)
CU
(CU)
(DN)
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