System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-61
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Data Synchronization Barrier operation
The purpose of the Data Synchronization Barrier operation is to ensure that all outstanding
explicit memory transactions complete before any following instructions begin. This ensures
that data in memory is up to date before the processor executes any more instructions.
The Data Synchronization Barrier Register is:
• a write-only operation
• accessible in both User and Privileged mode.
To access the Data Synchronization Barrier operation, write CP15 with:
MCR p15, 0, <Rd>, c7, c10, 4 ; Data Synchronization Barrier operation
For more information about memory barriers, see the ARM Architecture Reference Manual.
Data Memory Barrier operation
The purpose of the Data Memory Barrier operation is to ensure that all outstanding explicit
memory transactions complete before any following explicit memory transactions begin. This
ensures that data in memory is up to date before any memory transaction that depends on it.
The Data Memory Barrier operation is:
• write-only
• accessible in User and Privileged mode.
To access the Data Memory Barrier operation write CP15 with:
MCR p15, 0, <Rd>, c7, c10,5 ; Data Memory Barrier Operation.
For more information about memory barriers, see the ARM Architecture Reference Manual.
4.3.22 c9, BTCM Region Register
The BTCM Region Register characteristics are:
Purpose • Holds the base address and size of the BTCM.
• Determines if the BTCM is enabled.
Usage constraints The BTCM Region Register is:
• a read/write register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-41 on page 4-62.
Figure 4-40 shows the BTCM Region Register bit assignments.
Figure 4-40 BTCM Region Register bit assignments
Base address
31 12 11 7 6 2 1 0
Reserved Size
Reserved
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