Introduction
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 1-9
ID073015 Non-Confidential
1.5.1 Processor configurations
This section describes the processor arrangements supported and the functionality of each
arrangement. It contains the following sections:
• Single processor
• Redundant processor.
Single processor
This configuration includes a single processor.
Redundant processor
In this configuration, there is a single functional processor. The configuration also includes a
second redundant copy of the majority of the processor logic. The redundant logic is driven by
the same inputs as the functional logic. In particular, the redundant processor logic shares the
same cache RAMs as the functional processor. Therefore the processor requires only one set of
cache RAMs. The redundant logic operates in lock-step with the processor, but does not directly
affect the processor behavior in any way. The processor outputs to the rest of the system, and
the processor outputs to the cache RAMs, are driven exclusively by the functional processor.
During implementation, you can include comparison logic to compare the outputs of the
redundant logic and the functional logic. These comparators can detect a single fault that occurs
in either set of logic because of radiation or circuit failure. When used in conjunction with RAM
error detection schemes, you can protect the system from faults.
The input signals DCCMINP[7:0] and DCCMINP2[7:0] and the output signals
DCCMOUT[7:0] and DCCMOUT2[7:0] enable the comparators to communicate with the rest
of the SoC. Contact your system integrator for more information about these signals.
ARM provides example comparison logic, but you can change this during implementation. If
you are implementing a redundant processor configuration, contact ARM for more information.
TCM external errors ATCM external error enable ACTLR.ATCMECEN
BTCM external error enable, for B0TCM and B1TCM independently ACTLR.B0TCMECEN/
ACTLR.B1TCMECEN
TCM load/store-64
(read-modify-write) behavior
ATCM load/store-64 enable
b
ACTLR2.ATCMRMW
BTCM load/store-64 enable
b
ACTLR2.BTCMRMW
a. Can only be enabled if the appropriate TCM is configured with the appropriate error checking scheme, and the appropriate number of ports
b. Can only be enabled if the appropriate TCM is not configured with 32-bit ECC.
Table 1-2 Configurable options at reset (continued)
Feature Options Register field
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