Introduction
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 1-8
ID073015 Non-Confidential
Table 1-2 describes the various features that can be pin-configured to be either enabled or
disabled at reset. It also shows which CP15 register field provides software configuration of the
feature when the processor is out of reset. All of these fields exist in either the SCTLR, or one
of the auxiliary control registers.
BTCM at reset Disabled - Pin
Enabled
c
Base address configured
Base address
0x0
Build and pin
Peripheral ID
RevAnd field
Any 4-bit value - Build
AXI slave
interface
No AXI slave - Build
AXI slave included -
TCM Hard Error
Cache
No TCM Hard Error Cache - Build
TCM Hard Error Cache
included
d
-
Non-Maskable
FIQ Interrupt
Disabled. FIQ can be
masked by software.
-Pin
Enabled -
Parity type
e
Odd parity - Pin
Even parity -
a. The error scheme is a build option only. The number of BTCM ports (none, one, two) is set by both build and pin configuration.
b. Only available with the Cortex-R4F processor.
c. Only if the relevant TCM port(s) are included.
d. Only if at least one TCM port is included and uses ECC error checking.
e. Only relevant if at least one TCM port is included and uses parity error checking, one of the caches includes parity checking,
or AXI or TCM bus parity is included.
Table 1-1 Configurable options (continued)
Feature Options Sub-options
Build-configuration
or pin-configuration
Table 1-2 Configurable options at reset
Feature Options Register field
Exception endianness Little-endian/big-endian data for exception handling SCTLR.EE
Exception state ARM/Thumb state for exception handling SCTLR.TE
Exception vector table Base address for exception vectors:
0x00000000
/
0xFFFF0000
SCTLR.V
TCM error checking
ATCM parity check enable
a
ACTLR.ATCMPCEN
BTCM parity check enable, for B0TCM and B1TCM independently
a
ACTLR.B0TCMPCEN/
ACTLR.B1TCMPCEN
ATCM ECC check enable
a
ACTLR.ATCMPCEN
BTCM ECC check enabled, for B0TCM and B1TCM together
a
ACTLR.B0TCMPCEN/
ACTLR.B1TCMPCEN
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