ARM Cortex-R4 - Page 235

Level Two Interface
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-12
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STR or STM of one register
Table 9-10 shows the values of AWADDRM, AWBURSTM, AWSIZEM, and AWLENM for
an
STR or an STM that transfers one register (an STM 1) over the AXI master port to
Strongly-ordered or Device memory.
Note
A store of a word to Strongly-ordered or Device memory addresses 0x1 , 0x2 , 0x3 , 0x5 , 0x6 , or 0x7
generates an alignment fault.
STM of seven registers
Table 9-11 shows the values of AWADDRM, AWBURSTM, AWSIZEM, and AWLENM for
an
STM that writes seven registers (an STM 7) over the AXI master port to Strongly-ordered or
Device memory.
Note
A store-multiple to address 0x1 , 0x2 , 0x3 , 0x5 , 0x6 , or 0x7 generates an alignment fault.
Table 9-10 STR or STM1 to Strongly-ordered or Device memory
Address[2:0] AWADDRM AWBURSTM AWSIZEM AWLENM WSTRBM
0x0 (word0) 0x00 Incr 32-bit 1 data transfer b00001111
0x4 (word 1) 0x04 Incr 32-bit 1 data transfer b11110000
Table 9-11 STM7 to Strongly-ordered or Device memory to word 0 or 1
Address[4:0] AWADDRM AWBURSTM AWSIZEM AWLENM First WSTRBM
0x00 (word 0) 0x00 Incr 32-bit 7 data transfers b00001111
0x04 (word 1) 0x04 Incr 32-bit 7 data transfers b11110000