Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-24
ID073015 Non-Confidential
The breakpoint value contained in this register corresponds to either an instruction address or a
context ID. Breakpoints can be set on:
• an instruction address
• a context ID value
• an instruction address and context ID pair.
For an instruction address and context ID pair, two BRPs must be linked. A debug event is
generated when both the instruction address and the context ID pair match at the same time.
Table 12-16 shows the DBGBVR bit assignments.
• Only BRPn supports context ID comparison, where n+1 is the number of breakpoint
register pairs implemented in the processor.
• Bits [1:0] of Registers DBGBVR0 to DBGBVR(n-1) are Do Not Modify on writes and
Read-As-Zero because these registers do not support context ID comparisons.
• The contents of the CP15 Context ID Register give the context ID value for a DBGBVR
to match. For information on the CONTEXTIDR, see Chapter 4 System Control.
12.4.13 Breakpoint Control Registers
The DBGBCR Register characteristics are:
Purpose Contains the necessary control bits for setting:
• breakpoints
• linked breakpoints.
Usage constraints There are no usage constraints.
Configurations Available in all processor configurations.
Attributes See Table 12-17 on page 12-25.
Figure 12-10 shows the DBGBCR bit assignments.
Figure 12-10 DBGBCR Register bit assignments
Table 12-16 Breakpoint Value Registers functions
Bits Reset value Description
[31:0]
0x0
Breakpoint value
Reserved
M Linked BRP Reserved
Byte
address
select
Secure state access control
Breakpoint
address mask
Reserved
Reserved
B
31 29 28 24 23 22 20 19 16 15 14 13 9 8 5 4 3 2 1 0
S
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