ARM Cortex-R4 - Page 387

AC Characteristics
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. B-6
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Table B-6 shows the input timing parameters for the debug input ports.
Table B-7 shows the input timing parameters for the ETM input ports.
Clock uncertainty 60% AW PA RI T YS
Clock uncertainty 60% WPARITYS
Clock uncertainty 60% ARPARITYS
Table B-6 Debug input ports timing parameters
Input delay
minimum
Input delay
maximum
Signal name
Clock uncertainty 50% DBGEN
Clock uncertainty 50% NIDEN
Clock uncertainty 50% EDBGRQ
Clock uncertainty 50% PCLKENDBG
Clock uncertainty 50% PSELDBG
Clock uncertainty 50% PADDRDBG[11:2]
Clock uncertainty 50% PADDRDBG31
Clock uncertainty 50% PWDATADBG[31:0]
Clock uncertainty 50% PENABLEDBG
Clock uncertainty 50% PWRITEDBG
Clock uncertainty 10% DBGROMADDR[31:12]
Clock uncertainty 10% DBGROMADDRV
Clock uncertainty 10% DBGSELFADDR[31:12]
Clock uncertainty 10% DBGSELFADDRV
Clock uncertainty 50% DBGRESTART
Table B-7 ETM input ports timing parameters
Input delay
minimum
Input delay
maximum
Signal name
Clock uncertainty 50% ETMPWRUP
Clock uncertainty 50% nETMWFIREADY
Clock uncertainty 50% ETMEXTOUT[1:0]
Table B-5 AXI slave input port timing parameters (continued)
Input delay
minimum
Input
delay
maximum
Signal name