Revisions
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. E-4
ID073015 Non-Confidential
Table E-5 Differences between issue F and issue G
Change Location
Update introductory information Chapter 1 Introduction
Update register descriptions Chapter 3 Programmers Model
Chapter 4 System Control
Chapter 6 Events and Performance Monitor
Chapter 11 FPU Programmers Model
Chapter 12 Debug
Update debug register names Throughout book
Update undefined instruction example Undefined instruction on page 3-23
Update description of L1 memory access Table 4-34 on page 4-55
Update description of Slave Port Control Register c11, Slave Port Control Register on page 4-63
Update instruction prefetch description Controlling instruction prefetch and program flow
prediction on page 5-6
Update event bus interface description Event bus interface on page 6-19
Update description of store buffer draining Store buffer draining on page 8-19
Update AXI slave interface attributes AXI slave characteristics on page 9-22
Update Cache RAM access description Cache RAM access on page 9-26
Update the Revision field of the FPSID register Floating-Point System ID Register on page 11-5
Update the Revision field of the Peripheral ID Register 2
Peripheral ID Register 2 functions on page 12-40
Remove Programming and reading Integration Test Registers Chapter 13 Integration Test Registers
Update description of ATCEN1 signal Table A-6 on page A-11
Update description of COMMRX and COMMTX Table A-13 on page A-17
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