Camera Functional Description AW00097603000
24 Basler aviator GigE
4.1.1 Four Tap Sensor Digitization Mode
With four tap sensor digitization, the sensor is divided into quadrants, and a separate electronic
circuit is used to read out the pixels in each quadrant (see Figure 6 on page 25). Each of the
electronic circuits used to read out a quadrant of the sensor is referred to as a tap. The advantage
of the four tap digitization scheme is that it makes readout very fast because the four circuits are
used simultaneously to read out the sensor.
After a image has been captured (i.e., exposure has ended), the pixels in the sensor become ready
to be read out. At readout, the accumulated charges are transported from the pixels to the sensor’s
vertical shift registers. The charges from the top line of pixels in the array are then moved to the
upper horizontal shift register and the charges from the bottom line of pixels are moved to the lower
horizontal shift register as shown in Figure 6. Once this has been accomplished, the following
operations are performed simultaneously:
Charges from the left half of the top line are moved out of the upper horizontal shift register.
The left half of the upper horizontal shift register shifts out charges from left to right, that is,
pixel 1, pixel 2, pixel 3, and so on.
Charges from the right half of the top line are moved out of the upper horizontal shift register.
The right half of the upper horizontal shift register shifts out charges from right to left, that is,
pixel n, pixel n-1, pixel n-2, and so on (where n is the last pixel in a line).
Charges from the left half of the bottom line are moved out of the lower horizontal shift register.
The left half of the lower horizontal shift register shifts out charges from left to right, that is,
pixel 1, pixel 2, pixel 3, and so on.
Charges from the right half of the bottom line are moved out of the lower horizontal shift
register. The right half of the lower horizontal shift register shifts out charges from right to left,
that is, pixel n, pixel n-1, pixel n-2, and so on (where n is the last pixel in a line).
As the charges move out of the horizontal shift registers, they are converted to voltages proportional
to the size of each charge. Each voltage is then amplified by a Variable Gain Control (VGC) and
digitized by an Analog-to-Digital converter (ADC). For optimal digitization, gain and black level can
be adjusted by setting camera parameters.
After each voltage has been amplified and digitized, it passes through an FPGA and into an image
buffer. All shifting of charges from the vertical to the horizontal registers and out of the horizontal
registers is clocked according to the camera’s internal data rate. Shifting continues until all image
data has been read out of the sensor.
As the pixel data passes through the FPGA and into the buffer, it is reordered so that the pixel data
for each line is in ascending order from pixel 1 through pixel n.
The pixel data leaves the image buffer and passes back through the FPGA to an Ethernet controller
where it is assembled into data packets. The packets are then transmitted via an Ethernet network
to a network adapter in the host PC. The Ethernet controller also handles transmission and receipt
of control data such as changes to the camera’s parameters.
The image buffer between the sensor and the Ethernet controller allows data to be read out of the
sensor at a rate that is independent of the data transmission rate between the camera and the host
computer. This ensures that the data transmission rate has no influence on image quality.
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