Beck IPC SC123 User Manual

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 11
4.2 System Interface
Ball Pin
Name
Ball
Pin
Type
Description
CPUCLK
R8
OUT [24mA]
CPU Clock Output
This pin is driven from the output of the internal PLL.
If it used as output, don’t connect anything with more than 1pF
capacitive load ! See chapter 12.
PLLBYP#
L2
IN
PLL Bypass Input (Active LOW with Pull-up)
PLLBYP# is not supported anymore! See history, chapter 14.
This input, when pulled LOW, bypasses the internal PLL and uses
the CPUCLK pin as the source for the CPU.
WR#
T1
OUT [16mA]
Write Output (Active LOW with Pull-up)
This pin indicates that the current bus cycle is a memory or I/O write
cycle.
RD#
P2
OUT [16mA]
Read Output (Active LOW with Pull-up)
This pin indicates that the current bus cycle is a memory or I/O read
cycle.
WRH#
M1
OUT [16mA]
Write High Output (Active Low with Pull-up)
This pin indicates that the current bus cycle is a memory or I/O write
cycle and that the upper byte is being driven with valid data.
It can be used as BHE# (see chapter 5).
WRL#
L1
OUT [16mA]
Write Low Output (Active LOW with Pull-up)
This pin indicates that the current bus cycle is a memory or I/O write
cycle and that the lower byte is being driven with valid data.
It can be used as A0 (see chapter 5).
PIO17
(1)
HOLD
(1) (2)
D3
I/O [4mA]
IN
Hold (Active HIGH)
Hold is not supported anymore! See history, chapter 14.
This pin can be used as HOLD input. When driven HIGH by an
external bus master, the CPU responds with HLDA and releases the
bus for external use.
It can also be used as PIO[17].
HLDA
(2)
B1
OUT [4mA]
Hold Acknowledge (Active HIGH)
HLDA is not supported anymore! See history, chapter 14.
This pin goes HIGH to indicate the bus has been released for use by
an external bus master.
PIO6
(1)
ARDY
(1)
B3
I/O [4mA]
IN
Asynchronous Ready (Active HIGH)
This pin can be used with an external ready source. ARDY is double
synchronized internally using the falling edge of CPUCLK. It can be
used to extend external accesses.
It can also be used as PIO[6].
LCS#
(2)
D1
IN
Lower Chip Select (Schmitt Trigger Input Active LOW with Pull-up)
LCS# is not supported anymore! See history, chapter 14.
This pin is used by an external bus master to enable reading and
writing the internal SRAM.
RSTIN#
(1)
J1
IN
Reset Input (Schmitt Trigger Input, Active LOW with Pull-up)
This pin causes the CPU to perform a reset. When this pin is
asserted, the CPU immediately terminates any current bus cycles,
resets internal logic and prepares for executing code at the reset
address FFFFE0h.
RSTIN# is synchronized internally and extended internally to allow
~200 ms for the startup configuration (chapter 5) to settle to the
values driven by there individual resistors. This input is provided
with a Schmitt trigger to power-on via an RC network.
RSTOUT#
U1
OUT [4mA]
Reset Output (Active LOW)
This pin indicates whether the CPU is being reset. It indicates that
the internal logic is being reset and is to be used to reset any
external peripherals.

Beck IPC SC123 Specifications

General

Brand	Beck
Model	IPC SC123
Category	Controller
Language	English