IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 61
14 History
chapter 13., SnPb Reflow Profile added
additional information about CPUCLK
chapter 11.4, additional information about ETH0 LEDs
added chapter 11.5 and 11.6
added chapter 6.1, functional CPU description
chapter 6.3, more detailed SPI description
chapter 8.2.2 no 100MBit at 24MHz
chapter 4.1.5 JTAG Interface, TRST# with pull-up
chatper 6.2, UARTs added mark and space parity
chapter 6.2, added RTOS update information
chapter 10.2 additional hardware version on cover
chapter 4.2 System Interface, removed function CPUCLK
as input and PLLBYP# due to problems with external
clock sources.
CPUCLK is input only now. Leave PLLBYP#
unconnected.
chapter 4.2 System Interface, removed HOLD/HLDA and
LCS#. Tristate mode for SC186-EX is not supported
anymore.
chatper 4.1, updated pin description
chapter 8.3.2, chapter 8.3.3 ARDY timing updated
chapter 7.2, additional note to INT3
chapter 8.2.3, added input thresholds
chapter 11.2, additional ethernet example circuit
corrected example 2 in chapter 11.2
reset example 2 in chapter 11.2 to old schematic,
example 2 is not an error, it is an alternative schematic
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FITNESS FOR ANY PURPOSE.
BECK IPC GmbH Shall not is responsible for any errors that
may appear in this document. BECK IPC GmbH makes no
commitment to update or keep current the information
contained in this document.
Life critical applications — These products are not designed for
use in life support appliances, aeronautical applications or
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