Beck IPC SC123 - Reset Timing; ARDY Bus Timing

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IPC@CHIP SC123/SC143

Hardware Manual V1.06 [18.02.2010]

8.3.3 Reset timing

Figure 8-2: Reset Timing

8.3.4 Delaying system bus timing with external ARDY

NOTE:

To comply with the described ARDY behaviour, the following minimum wait state settings have to be

performed:

24 MHz CPU clock: 2 wait states

96 MHz CPU clock: 4 wait states

RSTIN#

RSTOUT#

RILROL

RILPW

CPUCLK

RIHROH

CHROH

CPUCLK is ignored while RSTIN# is driven low

CPUCLK

UCSOUT#

PCSx#

ARDY

CSARS

CLARH

Main Page

Table of Contents3
Overview7
Features8
Block Diagram9
Figure 3-1: Block Diagram9
Pin Description10
Pin Configuration10
Figure 4-1: Ball Grid Array Looking through Top of Package10
System Interface11
Table 4-1: Pin Description of System Interface12
Chip Selects13
Table 4-2: Pin Description of Chip Selects13
Dma14
Interrupts14
UART0 Interface14
Table 4-3: Pin Description of DMA Request Pins14
Table 4-4: Pin Description of Interrupts14
Table 4-5: Pin Description of UART014
UART1 Interface15
UART2 Interface15
Table 4-6: Pin Description of UART115
Table 4-7: Pin Description of UART215
I²C Bus16
Pure Pios16
Table 4-8: Pin Description of I²C Bus16
Table 4-9: Pin Description of Pure PIO Pins16
SPI Bus / UART317
Timers17
Table 4-10: Pin Description of SPI Bus / UART317
Table 4-11: Pin Description of Timers17
CAN Bus Interface18
USB Interface18
JTAG Interface18
Table 4-12: Pin Description of CAN Bus18
Table 4-13: Pin Description of USB18
Table 4-14: Pin Description of JTAG18
Ethernet 0 Interface (Internal PHY)19
MII Ethernet 1 Interface (External PHY)19
Table 4-15: Pin Description of Internal PHY19
Table 4-16: Pin Description of MII19
PHY Power (Internal PHY)20
Power20
Table 4-17: Pin Description of PHY Power Pins20
Table 4-18: Pin Description of Power Pins20
Programmable I/O Pins21
Table 4-19: List of PIO Sharing Designations21
System Start-Up Configuration22
PIO Pins22
Address Pins22
PFI Pin23
Figure 5-1: Power on Flowchart with Power Fail Interrupt Enabled23
Functional Description24
Cpu24
Registers24
Table 6-1: General Purpose Registers24
Table 6-2: Segment, Status and Control Registers24
Memory Organization25
24-Bit Address Mode25
Figure 6-1: 24-Bit Address Generation25
Figure 6-2: Contiguously Segments in Memory25
Table 6-3: Segment Register Selection Rules25
Peripheral Accesses through the Address-/Databus26
Figure 6-3: 8 Bit Read Access from C00 , CSBE = 0, Read = 0X5526
Figure 6-4: 16 Bit Read Access from C00 , CSBE = 0, Read = 0X123426
Figure 6-5: 16 Bit Read Access from C01 , CSBE = 0, Read = 0X567827
Figure 6-6: 8 Bit Read Access from C01 , CSBE = 0, Read = 0X5527
Figure 6-7: 8 Bit Write Access to C00 , CSBE = 0, Write = 0X2328
Figure 6-8: 16 Bit Write Access to C00 , CSBE = 0, Write = 0X123428
Figure 6-9: 16 Bit Write Access to C01 , CSBE = 0, Write = 0X567829
Figure 6-10: 8 Bit Write Access to C01 , CSBE = 0, Write = 0X2329
Figure 6-11: 8 Bit Write Access to C00 , CSBE = 1, Write = 0X2330
Figure 6-12: 8 Bit Write Access to C01 , CSBE = 1, Write = 0X2330
Figure 6-13: 16 Bit Write Access to C00 , CSBE = 1, Write = 0X123431
Figure 6-14: 16 Bit Write Access to C01 , CSBE = 1, Write = 0X567831
Uarts32
RTOS Update Via Serial Ports32
Spi33
Table 6-4:Context between SDO and SDI to MOSI and MISO in Different Modes34
Can36
Introduction36
Table 6-5: Provided CAN Baud Rates36
TX Channels37
RX Channel37
Figure 6-15: TX Message Routing37
Usb38
Figure 6-16: Pullup-/Down Resistors for USB Full-Speed Device38
Power Fail Interrupt39
Description39
Storing Non-Volatile Data to Internal Flash Memory39
Storing Non-Volatile Data to External Memory39
Mapping External Memory40
MII Interface40
Figure 6-17: Sketch of the Logic to Decode the Chip Select for an External Memory40
Table 6-6: Truth Table of FLSSEL and UCSOUT# and External Memory40
Timers41
Reset41
Figure 6-18: Internal Reset Processing41
System Overview42
Memory Map42
Figure 7-1: Memory Map42
System Interrupts43
Watchdog43
Characteristics44
Absolute Maximum Ratings44
Recommended Operating Ranges44
Voltage and Temperature44
Supply Current44
Table 8-1: Absolute Maximum Ratings44
Table 8-2: Recommended Operating Ranges44
Table 8-3: Supply Current44
Inputs45
Outputs45
Programmable Input/Output Pins45
XIN/XOUT Pins45
Table 8-4: Inputs45
Table 8-5: Outputs45
Table 8-6: Pios45
Table 8-7: 3. I/O Characteristics Xin/Xout Pins45
PHY Receiver Input Characteristics46
100Base-TX Transceiver Characteristics46
Table 8-8: PHY Receiver Input Characteristics46
Table 8-9: 100Base-TX Transceiver Characteristics46
AC Characteristics47
Timing Parameter List47
Table 8-10: AC Characteristics47
System Bus Timing48
Figure 8-1: System Bus Timing48
Reset Timing49
Figure 8-2: Reset Timing49
Routing and Placement Rules50
PCB Board Design Suggestion for SC123/SC14350
Figure 9-1: PCB Board Design Suggestion50
Figure 9-2: PCB Board Design Suggestion50
Routing and Placement Rules for Ethernet Components51
Suggested Magnetics51
Package Information52
Dimensions52
Figure 10-1: Package Dimensions52
Table 10-1: Package Dimensions52
Cover Description53
Figure 10-2: Cover53
Application Examples54
Minimum Circuit Requirements54
Figure 11-1: Minimum Circuit Requirements for Sc1X354
Ethernet Example Circuit55
Figure 11-2: Ethernet Example Circuit 155
External Memory56
Figure 11-3: Example Circuit for Connecting an External Memory56
Traffic/Link/Speed Leds57
Figure 11-4: Circuit Example for Two Bi-Coloured Leds57
Figure 11-5: Circuit Example for Four Mono-Coloured Leds57
Sc1X3 Socket58
Custom Series Programming of Sc1X358
Figure 11-6: Sc1X3-Socket58
CPUCLK Handling59
Reflow Profile60
Figure 13-1: Reflow Profile60
Table 13-1: Typical Reflow Profile Conditions60
History61

Beck IPC SC123 - Reset Timing; ARDY Bus Timing

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