IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 40
6.8 Mapping external memory
The RTOS provides the integration of external memory into the internal memory architecture. Through FLSSEL
and UCSOUT# a chip select for an external memory can be generated. FLSSEL is driven low automaticly, if
memory in 0x800000 - 0xFFFFFF is accessed by the user. FLSSEL don’t need any software initialization.
The default connection (UCSIN# connected to UCSOUT#) has to be opened and decoded with some simple
logic.
Figure 6-17: Sketch of the logic to decode the chip select for an external memory
Attention: If code runs in the external memory, accesses to the filesystem will lead into a system crash.
Any memory can be mapped, e.g. a SRAM, NV-SRAM, DPRAM, memory mapped I/O, etc.
Table 6-6: Truth Table of FLSSEL and UCSOUT# and external memory
An example for designing hardware is shown in chapter 11.3.
6.9 MII Interface
The SC1x3 provides two Ethernet controllers. The first Ethernet controller (MAC0) is connected to interrupt 0
(INT0) and has the internal PHY connected to it.
The second Ethernet controller (MAC1) is connected to interrupt 1 and is shared with the external interrupt 1.
This Ethernet controller connects to an MII port (Media Independent Interface). The main function of this
interface is to provide a communication path between the internal MAC and an external PHY.
000000h.. 7FFFFFh
800000h.. FFFFFFh
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