IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 33
6.3 SPI
SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed
length (one to eight bits) to be shifted into and out of the device at a programmable bit-transfer rate.
SPI is an industry-standard communications interface that does not have specifications or a standards
organizing group. As a result, there are no licensing requirements. Because of its simplicity, SPI is commonly
used in embedded systems. Many semiconductor manufacturers sell a variety of sensor, conversion, and
control devices that use SPI.
SC1x3 SPI Controller
The SC1x3 SPI controller shares an interrupt with the I²C controller and connects to interrupt 2. The SPI
controller is enabled through the RTOS API.
The SPI bus is a 3-wire serial bus that links a serial shift register between a master device and a slave device.
The SC1x3 supports both, master and slave operations (not at the same time). Typically, master and slave
devices have an 8-bit shift register. During an SPI transfer, master and slave shift their registers by eight bits
and exchange their 8-bit register values, starting with the most significant bit.
The SPI interface is software configurable. The clock polarity, clock phase, SLVSEL (Slave Select) polarity,
clock frequency in master mode, and number of bits to be transferred are software programmable. SPI supports
multiple slaves on a single 3-wire bus by using separate Slave Select signals to enable the desired slave.
Multiple masters are also fully supported and some support is provided for detecting collisions when multiple
masters attempt to transfer at the same time.
A Wired-OR mode is provided which allows multiple masters to collide on the bus without risk of damage. In
this mode, an external pull-up resistor is required on the Master Out Slave In (MOSI) and Master In Slave Out
(MISO) pins. The wired-OR mode also allows the SPI bus to operate as a 2-wire bus by connecting the MOSI
and MISO pins to form a single bi-directional data pin. Generally, pull-ups are recommended on all of the
external SPI signals to ensure they are held in a valid state, even when the SPI interface is disabled.
In SPI master mode the SC1x3 uses a 16-bit counter to divide the CPU clock and uses the result to generate
SCK. In SPI slave mode, an SPI interrupt occurs when the SLVSEL pin transitions from active to inactive.
When operating as a slave, the SPI clock signal (SCK) must be slower than 1/16th of the CPU clock.
Attention: The SC1x3 is not capable to receive or send continous with a clock rate of 1/16 CPU in slave mode.
This would cause to heavy interrupt load and would lead into a system crash.
The maximum clock frequency in master mode is 48MHz.
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