IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 34
Note: The SPI is fully synchronous to the CLK signal. As a result, SCK is sampled and then operated on. This
results in a delay of 3 to 4 clocks, which may violate the SPI specification if SCK is faster than 1/8th of the CPU
clock. In master mode, the SPI operates exactly on the proper edges, since the SPI controller is generating
SCK.
The SPI controller has an enhanced mode called Autodrive. It is valid in master mode. In this mode, the
SLVSEL pin is driven active when data is written to the data register. The polarity of SLVSEL is selectable.
The definition of the pins SDO and SDI is depending on the master/slave configuration of the SC1x3. In
addition, it’s possible to swap the configuration through SPI_ALTERNATE_IO (see RTOS API).
For using the function Autodrive to automaticly drive the Slave Select SPI_ALTERNATE_IO has to be set (see
RTOS API).
The following table describes the context:
Table 6-4:Context between SDO and SDI to MOSI and MISO in different modes
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