IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 59
12 CPUCLK handling
CPUCLK is a sensitive signal. It should be handled very careful. Here are some suggestions and restrictions.
CPUCLK should never be loaded with more than 1pF.
Rising and falling slopes of CPUCLK should never be slower then 1ns in an application.
Measuring of CPUCLK with normal passive probes loads CPUCLK, so when it is loaded with more than
1pF, the slopes will be slower than 1ns.
For measurements under circumstances of laboratories CPUCLK can be used for triggering or measuring
other signals. Loading of CPUCLK with more than 1pF will cause no hardware defect. But be careful, it
reacts very sensitive to ESD.
If slopes of CPUCLK are slower than 1ns, the properly working of the internal SDRAM is not guaranteed.
To use CPUCLK in an application, buffering is necessary. A buffer with low input capacity should be used,
e. g. 74AUP1G34.
A resistor can be profitable in series of CPUCLK and an input of an IC. The value of the resistor should be
120 ohm minimum. It depends on what specific parameters the input has. In case of the resistor is used, the
speed of the slopes should be measured through an active probe and an oscilloscope which is fast enough,
to measure such fast signals.
The Layout of a PCB can have influences to CPUCLK. Route CPUCLK as short as possible.
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