HL-1850/1870N SERVICE MANUAL
3-3
1.3 Main PCB
For the entire circuit diagram of the main PCB, see APPENDIX 2. to 7. MAIN PCB CIRCUIT
DIAGRAM, HL-1850/1870N in this manual.
1.3.1 ASIC
A Fujitsu 32bit RISC CPU, MB86834 (SPARC lite) is built in the ASIC. While the CPU is driven
with a clock frequency of 48 MHz in the user logic block, it itself runs at 96 MHz, which is
generated by multiplying the source clock by two.
The functions of the interface block communication with external devices are described below;
(1) IEEE1284
Stores the data received from the PC into DRAM as controlled by the DMA controller. It is
applicable to both normal receiving and bi-directional communication (nibble mode, byte
mode, ECP mode).
Fig. 3-3
HL-1850
HL-1870N
To Next Page
Loading...
