The DW1000 parameters that may be read and written using these SPI transactions are detailed in section 7
– The DW1000 register set.
2.2.2 Interrupts
The DW1000 can be configured to assert its IRQ pin on the occurrence of one or more status events. The
assertion of the IRQ pin can be used to interrupt the host controller and redirect program flow to deal with
the cause of the event.
The polarity of the IRQ pin may be configured via the HIRQ_POL bit in the Register file: 0x0D – System
Control Register. By default on power up the IRQ polarity is active high. This is the recommended polarity to
ensure lowest power operation of the DW1000 in SLEEP and DEEPSLEEP device states. This pin will float in
SLEEP and DEEPSLEEP states and may cause spurious interrupts unless pulled low.
The occurrence of a status event in Register file: 0x0F – System Event Status Register may assert the IRQ pin
depending on the setting of the corresponding bit in the Register file: 0x0E – System Event Mask Register.
By default, on power-up, all interrupt generating events are masked and interrupts are disabled.
2.2.3 General Purpose I/O
The DW1000 provides 8 GPIO pins. These can be individually configured at the user’s discretion to be inputs
or outputs. The state of any GPIO configured as an input can be read and reported to the host controller
over the SPI interface. When configured as an output the host controller can set the state of the GPIO to
high or low.
Some of the GPIO lines have multiple functions as listed in the DW1000 data sheet.
The configuration and operation of the GPIO pins is controlled via Register file: 0x26 – GPIO control and
status.
By default, on power-up, all GPIOs are configured as inputs.
2.2.4 The SYNC pin
This pin is used for external clock synchronisation purposes. See section 6.1 – External Synchronisation for
further details.
2.3 DW1000 Operational States
2.3.1 State diagram
The DW1000 has a number of different operational states (or modes). These are listed and described in
Table 1 below and the transitions between them are illustrated in Figure 8.
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