Description of fields within Register file: 0x0D – System Control Register
WAIT4RESP
reg:0D:00
bit:7
Wait for Response. The WAIT4RESP control works in conjunction with TXSTRT bit above and
the W4R_TIM value in Register file: 0x1A – Acknowledgement time and response time. When
WAIT4RESP is set at the same time as the TXSTRT then when the DW1000 has finished
transmitting the frame it will automatically turn-around, disabling the transmitter and enabling
the receiver, to await a response frame. The W4R_TIM value may be programmed with a
delay between TX end and RX enable. Delaying turning on the receiver will save power in
cases where the response is known to be a delayed by a certain amount. The WAIT4RESP bit
will clear at the time when DW1000 enables the receiver, (or when a TRXOFF is employed).
NB: When in use the WAIT4RESP bit must be set at the same time as the TXSTRT bit is set, (i.e.
by the same write).
Enable Receiver. This bit commands the DW1000 to turn on its receiver and begin looking for
the configured preamble sequence. It is assumed that the all necessary configurations have
been made before turning on the receiver. For a general discussion of reception see section 4
– Message Reception. The RXENAB bit will clear as soon as the DW1000 sees it and initiates
reception. NB: The receiver has a delay of 16 µs after issuing the enable receiver command,
after which it will start receiving preamble symbols.
Receiver Delayed Enable. This control works in conjunction with RXENAB and the DX_TIME
value specified by Register file: 0x0A – Delayed Send or Receive Time. When the user wants to
control the time of turning on the receiver, the turn on time is programmed into DX_TIME, and
then both RXDLYE and RXENAB should be set to correctly invoke the delayed receiving feature.
The DW1000 then precisely controls the RX turn on time so that it is ready to receive the first
symbol of preamble at the specified DX_TIME start time. In cases when the received time can
be known precisely, for example when a response is expected at a well-defined time,
employing RXDLYE will give a power saving as it allows the IC to remain idle until the moment
it is required to act for the reception.
Host Side Receive Buffer Pointer Toggle. In the doubly buffered receiver mode the host uses
this bit to change which of the buffer pairs it is reading from. The half being accessed is
reported by the HSRBP (Host Side Receive Buffer Pointer) status bit in Register file: 0x0F –
System Event Status Register. See section 4.3 – Double Receive Bufferfor more details.
7.2.16 Register file: 0x0E – System Event Mask Register
System Event Mask Register
Register map register file 0x0E is the system event mask register. These are aligned with the event status
bits in the SYS_STATUS register. Whenever a bit in the SYS_MASK is set (to 1) and the corresponding bit in
the SYS_STATUS register is also set, then an interrupt will be generated asserting the hardware IRQ output
line. The interrupt condition may be removed by clearing the corresponding bit in this SYS_MASK register
(by setting it to 0) or by clearing the corresponding latched bit in the SYS_STATUS register (generally by
writing a 1 to the bit – please refer to individual SYS_STATUS register bit definitions for details).
The SYS_STATUS register contains the system event status bits identified and described below:
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