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decaWave DW1000 - 7 The DW1000 register set; Register map overview

decaWave DW1000
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DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 63 of 242
7 The DW1000 register set
The DW1000 is controlled by an associated host microcontroller system using the SPI interface to access a
series of registers within the device. The DW1000 register set includes configuration registers, status
registers, control registers, data buffer registers, and diagnostic registers. Section 2.2 The SPI Interface
described the SPI interface and the low level transactions for reading and writing the parameters of the
DW1000. This section begins with 7.1 Register map overview and then 7.2 Detailed register description,
where each individual parameter is described in detail.
7.1 Register map overview
The register map overview is given in Table 15. This lists the registers in address order, by register file ID,
giving the register file length in octets, its type (RO = Read-Only, RW = Read & Write, SRW = Special Read
Write see individual register descriptions for details about how the Read/Write access is special), and a
brief high level description of the register. Section 7.2 gives a detailed description of each register.
Note: When writing to any of the DW1000 registers care must be taken not to write beyond the published
length of the selected register and not to write to any of the reserved register locations. Doing so may cause
the device to malfunction.
Table 15: Register map overview
ID
Length
(octets)
Type
Mnemonic
Description
0x00
4
RO
DEV_ID
Device Identifier includes device type and revision info
0x01
8
RW
EUI
Extended Unique Identifier
0x02
-
-
-
Reserved
0x03
4
RW
PANADR
PAN Identifier and Short Address
0x04
4
RW
SYS_CFG
System Configuration bitmap
0x05
-
-
-
Reserved
0x06
5
RO
SYS_TIME
System Time Counter (40-bit)
0x07
-
-
-
Reserved
0x08
5
RW
TX_FCTRL
Transmit Frame Control
0x09
1024
WO
TX_BUFFER
Transmit Data Buffer
0x0A
5
RW
DX_TIME
Delayed Send or Receive Time (40-bit)
0x0B
-
-
-
Reserved
0x0C
2
RW
RX_FWTO
Receive Frame Wait Timeout Period
0x0D
4
SRW
SYS_CTRL
System Control Register
0x0E
4
RW
SYS_MASK
System Event Mask Register
0x0F
5
SRW
SYS_STATUS
System Event Status Register
0x10
4
ROD
RX_FINFO
RX Frame Information
(in double buffer set)
0x11
1024
ROD
RX_BUFFER
Receive Data
(in double buffer set)
0x12
8
ROD
RX_FQUAL
Rx Frame Quality information
(in double buffer set)
0x13
4
ROD
RX_TTCKI
Receiver Time Tracking Interval
(in double buffer set)
0x14
5
ROD
RX_TTCKO
Receiver Time Tracking Offset
(in double buffer set)

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